The present invention relates to a field-effect transistor. More particularly, it relates to a power field-effect transistor of which high voltage operation is required and to a manufacturing method therefor.
For the achievement of diversified means for communication and improved quality thereof, analog signal modulation techniques have been replaced by digital signal modulation techniques. In the field of radio communication, the use of higher frequencies has spread more rapidly than ever. With the recent RF device developments in communication represented by a mobile telephone, there has been greater demand for field-effect transistors using gallium arsenide (GaAs) due to their low-noise and low-distortion properties suitable for digital communication and their high-speed and high-frequency properties superior to those of silicon devices. In particular, a power FET used in a transmission amplifier has been widely utilized to take advantage of GaAs consuming low power.
An important issue for the power FET is higher voltage operation, and consequently higher breakdown voltage. The breakdown voltage of the power FET is determined by the concentration of an impurity in a region immediately below a gate electrode and the distance between the gate and drain electrodes. Naturally, the breakdown voltage is higher as the impurity concentration is lower or the distance between the gate and drain electrodes is larger. With a MESFET (Metal Semiconductor FET) in which a channel region is formed by implanting ions into a substrate and a gate electrode is formed directly on the channel region, high breakdown voltage cannot be achieved due to a high impurity concentration in the region immediately below the gate electrode. With a MESFET in which an undoped layer composed of an epitaxial film containing no impurity is formed immediately under a gate electrode, high breakdown voltage can be achieved due to a low impurity concentration in a region immediately below the gate electrode.
Referring to the drawings, a conventional MESFET comprising an undoped layer between a gate electrode and a channel layer will be described.
FIG. 7 shows a cross-sectional structure of the conventional MESFET using GaAs. As shown in the drawing, a channel layer 92 made of n-type GaAs doped with Si as an impurity and an undoped layer 93 made of GaAs or AlGaAs are formed sequentially on a semi-insulating substrate 91 made of GaAs. A pair of contact layers 94 made of n-type GaAs highly doped with Si as an impurity are formed on the undoped layer 93 to have a given gap therebetween. A source electrode 97 and a drain electrode 98 each made of deposited AuGe or the like are formed on the respective contact layers 94. A gate electrode 99 made of deposited Al or the like is formed on the undoped layer 93 between the source and drain electrodes 97 to make Schottky contact with the undoped layer 93.
Since the undoped layer 93 is provided between the gate electrode 99 and the channel layer 92 in the conventional MESFET, the absolute breakdown voltage thereof is improved. On the other hand, a maximum breakdown voltage for the drain electrode is not considerably improved due to an electric field localized to the region underlying the edge portion of the gate electrode 99 closer to the drain electrode 98. To achieve higher value, therefore, the distance between the gate and drain electrodes should be increased because the maximum breakdown voltage for the drain electrode is dependent only on the distance between the gate and drain electrodes. However, the increased distance between the gate and drain electrodes increases a resistance between the gate and drain electrodes as well as the on-resistance of the FET, which degrades the characteristics of the FET.
Under the circumstances under which the phenomenon of avalanche breakdown that determines the value of breakdown voltage occurs, numerous electron-hole pairs are generated in the region of the channel layer 92 underlying the edge portion of the gate electrode 99 closer to the drain electrode 98 and eventually cause a runaway effect in the FET. Thus, higher breakdown voltage is incompatible with improvements in other electric properties, while stable operation cannot be performed with voltage close to a maximum breakdown value.